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| RapidChip Basics of Design Collapse summary A platform ASIC fills the design gap between the full cell-based ASIC
design, which typically requires about 25 masks and a 12- to 18-month
design cycle, and the in-system instantly configurable and off-the-shelf
field-programmable gate array. Platform ASICs and their cousins, the structured
ASICs, often can provide a lower-cost solution than a cell-based design
when component volumes are a few hundred thousand units or less. As an
alternative to the high-complexity FPGAs, the platform ASIC also can offer
significant cost reductions once a design is 脙垄脗聙脗聍locked in脙垄脗聙脗聺 and
unit volumes approach 5000 or more. Nonrecurring engineering charges are
significantly lower than they are for cell-based designs as well, since
only a few metal-mask layers must be customized versus the 25 or so layers
a cell-based ASIC requires. Collapse summary
<< Revise the query This Datasheet provides reference information for the 0.11 μm Enhanced
SFI-4 (ESFI-4)Transceiver Hardmacro, including an architectural description,
signal descriptions, and functional timing information. The 0.11 μm Enhanced
SFI-4 (ESFI-4)Transceiver Hardmacro is a CoreWare? intellectual property
(IP) block that is delivered as a diffused hardmacro. It is an enhanced
duplex transmit and data interface core that supports the OIF SERDES-to-Framer
Interface Level 4 (SFI-4) definition for line side SONET communications
standards. As well as conforming to the XSBI line side definitions in
the IEEE 802.3ae 10GEthernet Specification it has been enhanced to also
support OC-48 applications. Collapse summary This datasheet provides a basic overview of the cw000733_1_0 DDR2 PHY
CoreWare IP, including features and benefits, a block diagram, functional
unit overview, list of signals, register summary, instruction set summary,
and electrical and mechanical specifications. The cw000733_1_0 DDR2 PHY
CoreWare IP is a complete physical interface between a Memory Controller
(which may be on or off the Platform ASIC slice) and external SDRAM memory
devices. Collapse summary This datasheet provides a basic overview of the 0.11μm Processor System
for ARM926EJ-S, including features and benefits, a block diagram, functional
unit overview, list of signals, register summary, instruction set summary,
and electrical and mechanical specifications. This fully integrated, general
purpose system is built from existing LSI Logic CoreWare? IP blocks and
delivered as a Fixed IP block. Expansion ports let you add external features
and application-specific hardware to the subsystem. Collapse summary This Datasheet provides reference information for the 0.11μm Wide Range
18-Channel HyperPHY CoreWare, including an architectural description,
signal descriptions, and functional timing information. The 0.11μm Wide
Range 18-Channel HyperPHY is a CoreWare? intellectual property (IP) block
that is delivered as a diffused hardmacro. This product is RapidPrimed?
certified. The Wide Range 18-Channel HyperPHY CoreWare architecture provides
an 18-channel data transmit hardmacro and an 18-channel data receive hardmacro
both with integral clock generation and timing control. Transmit and receive
channels operate independently, but may be synchronized. The integration
of these two hardmacro blocks, diffused onto a RapidChip Integrator or
Extreme family ASIC slice, make up the Wide Range 18-Channel HyperPHY.
External interface is through the slice's LVDS I/O. Collapse summary This technical manual provides detailed reference information for the
1394 Lead Vehicle, including a functional description, register and signal
descriptions, physical and electrical specifications, and functional timing
information. The 1394 Lead Vehicle is an IEEE1394 I/O processor. It is
IEEE1394-a compliant (400 Mbit/s), and also contains an OHCI-compliant
USB 1.1 host controller. The 1394 Lead Vehicle gluelessly interfaces to
the LSI Logic SC2000 set-top box source decoder. Collapse summary This technical manual provides detailed reference information for the
1394 Link Layer Controller Core, including a functional description, register
and signal descriptions, and functional timing information. The 1394 Link
Layer Controller Core is an IEEE1394a compliant PHY/link interface with
up to eight data lines for 400 Mbit/s operation. Collapse summary The 1394 Node Controller Core is fully IEEE 1394a-2000 compliant that
easily interfaces into existing CPU bus and DMA engine architecture supporting
a wide range of devices, including Set-top Boxes, Digital TV, gaming consoles,
PCs and PC peripherals. Collapse summary This user's guide provides detailed reference and usage information for
the 1394 Node Controller Core SVE (Silicon Verification Environment),
including a functional description and a list of deliverables. The 1394
Node Controller Core SVE is a set of Verilog RTL files that allow you
to simulate the 1394 connection to a chip containing the 1394 Node Controller.
Collapse summary This technical manual provides detailed reference information for the
1394 Node Controller Core, including a functional description, register
and signal descriptions, and functional timing information. The 1394 Node
Controller Core is a IEEE1394-1995/IEEE1394a compliant core that provides
full link layer functionality and interfaces with any 1394a-compliant
PHY. Collapse summary This technical manual provides detailed reference information for the
1394 Physical Layer (PHY) Core, including a functional description, register
and signal descriptions, and functional timing information. The 1394 Physical
Layer (PHY) Core is an IEEE1394-1995 and 1394a-2000 PHY core. It supports
PHY/Link and cable interfaces with data transmission speeds of 100, 200,
and 400 Mbits/s. The core is offered in the G12?-p process technology
as a 2-port (CW006002) or 3-port (CW006003) hardmacro. Collapse summary LSI Logic offers the ARM926EJ-S synthesized processor core as a RapidReadyTM
hardmac for the Landing ZoneTM region in the RapidChipTM Integrator slices
and a RapidReadyTM diffused core in select RapidChip Foundation slices.
By choosing a diffused or hardmac implementation of the ARM926EJ-S, SOC
designers eliminate the risk associated with closing timing and can get
a processor that芒聙聂s pre-optimized for maximum performance. At 200MHz,
these implementations match key memory frequencies and further enable
maximum system performance. Collapse summary LSI Logic offers the MIPS64 5Kf processor core (CW004252) synthesized
onto our GflxTM 0.11μm (drawn) high performance process technology, supporting
clock frequencies of up to 300 MHz. Collapse summary The LSI Logic implementation of the MIPS32 24kf processor is a 440 MHz
timing closed hardmac that eliminates the effort and risk of closing processor
timing at the ASIC level. It includes a 32k instruction and 32k data cache,
hardware floating point support for the IEEE 754 standard, a 32x32 integer
multiplier, a memory management unit (MMU) with a 32 entry translation
lookaside buffer (TLB) and two sets of shadow registers. It also includes
the MIPS Technologies CorExtend capability that enables designers to add
their application-specific instructions while maintaining full compliance
with the MIPS32 architecture. Collapse summary Six GB/s (Gigabits per second) applications will begin to dominate the
market in late 2005. Because of the continuing pressure from their customers
to upgrade their data bandwidth, service providers need to consider how
to sate this demand. LSI Logic's 6G HyperPHY SerDes enables equipment
providers to drive these legacy backplanes at rates greater than 6Gb/s
per signal pair. Collapse summary This technical manual provides detailed reference information for the
80C300 10/100 Fast Ethernet Controller, including a functional description,
register and signal descriptions, physical and electrical specifications,
and functional timing information. The 80C300 10/100 Fast Ethernet Controller
is a full-duplex single-channel 10/100 Mbit/s Ethernet data link controller
(MAC). The 80C300 operates in either 10 Mbit/s serial mode or as a 10/100
Mbit/s programmable MII interface. The MII interface allows glueless connection
to PHY devices. Collapse summary A paper presented by Mint Technology at the 2003 DVCon. The paper describes
how Mint Technology developed a verification environment to verify an
ARM Based ASIC. The environment takes advantage of POSIX threads and the
Verilog PLI to allow easier and more robust testing. Collapse summary A paper presented by Mint Technology at IVC/VIUF 1998 (International
Verilog HDL Conference). The paper describes how Mint Technology built
a verification tool and methodology to allow functional tests to be written
in C. Collapse summary A paper presented by Mint Technology at IVC/VIUF 1998 (International
Verilog HDL Conference). The paper describes how Mint Technology built
a verification tool and methodology to allow functional tests to be written
in C. Collapse summary This datasheet provides a basic overview of the AMBA Reference Design,
including features and benefits, a block diagram, functional unit overview,
list of signals, register summary, instruction set summary, and electrical
and mechanical specifications.This fully integrated, general purpose system
is built from existing LSI Logic CoreWare IP blocks and delivered as a
Soft IP block. Collapse summary The ARM 1026EJ-S macrocell, licensed from ARM? Limited, is a fully synthesized
processor core delivering new levels of performance, functionality and
flexibility to enable innovative SoC applications. The high performance
32-bit RISC core has extensive 64-bit bussing, and includes Jazelle? technology
from ARM for Java acceleration. Collapse summary The ARM1136J-S macrocell, licensed from ARM? Limited, is a fully synthesized
processor core featuring an industry leading combination of high-performance,
low-power, small size, and high code density, to address next generation
high performance SoC applications. The high performance 8-stage pipeline
32-bit RISC core has extensive 64-bit bussing, and includes Jazelle? technology
from ARM for Java acceleration. The LSI with Gflx implementation of the
ARM 1136J-S core has 16K byte instruction and data caches, 16K/16K instruction
and data tightly coupled memories (TCMs), and a memory management unit
(MMU). Collapse summary LSI Logic offers the ARM1136J-S processor core synthesized onto its Gflx"
0.11 micron (drawn) high-performance process technology, supporting clock
frequencies of up to 425MHz. The ARM1136J-S macrocell, licensed from ARM
Limited, is a fully synthesized processor core featuring an industry leading
combination of high-performance, low-power, small size, and high code
density, to addresss next generation high-performance SoC applications.
The high-performance 8-stage pipeline 32-bit RISC core has extensive 64-bit
bussing, and includes Collapse summary The LSI Logic implementation of the ARM1156T2-S processor for cell-basedASIC
provides an integration friendly solution for applications like mass storagedevices
that require the deterministic performance of Tightly Coupled Memories(TCM).
This implementation of the ARM1156T2-S processor is a timing-closedhardmac
that runs at 450 MHz and provides a higher-performance option tothe ARM966E-S
processor with minimal increase in cost. As a member of theCoreWare? IP
library this core will integrate seamlessly with the ASIC designflow and
will help ensure a right-first-time SOC design. Collapse summary This document explains errata related to ARM926. Collapse summary The ARM926EJ-S is a five-stage pipeline, Harvard cache architectur processor
including the embedded Jazelle? Java? technology from ARM?. It contains
a complete processor subsystem comprising a memory management unit (MMU),
instruction and data caches, and instruction and data tighly coupled memory
(TCM) interfaces. The core also includes an Embedded Trace Macrocell (ETM)
interface, a co-processor interface, and separate instruction and data
AMBA (Advanced Microprocessor Bus Architecture) AHB (Advanced High Performance
Bus) interface units. This high level of integration helps ease the task
of integrating the core into a System-on-Chip (SoC) design. Collapse summary The CW001102 processor core is a low power implementation of the popular
ARM966E-S, synthesized onto LSI Logics G12 0.18 micron low leakage process
technology. Collapse summary The CW001105 processor core is a 200 MHz implementation of the popular
ARM966E-S, synthesized onto LSI Logics G12 0.18 micron high performance
process technology. Collapse summary Is the answer to the reuse dilemma configurable intellectual property,
modifiable IP or both? The debate has become a heated one because both
sides are right. Collapse summary Originally presented at the Club Verification 2003 conference by one
of Mint Technology's top verification engineers. The paper describes how
a single verification environment can tackle the challenges of both block
and system-level testing. Collapse summary Fourth Generation High Performance Multi-Gigabit/s CMOS Transceiver Cores.
LSI Logic's GigaBlaze? cores are the first multi-gigabit per second CMOS
transceiver cores in the industry. They provide a full-duplex, point-to-point
communications channel for gigabit speed serial interfaces. Protocol independence
enables the cores to be used with standard high-speed communications protocols
to create a high-speed serial interfaces. Applications for the cores include
storage subsystems, network switches and routers, System Area Networks
(SAN) and high-speed backplanes. Collapse summary LSI Logic's GigaBlaze cores provide a full duplex, point-to-point communications
channel for multi-gigabit serial interfaces. The cores may be used with
a number of standard high-speed communications protocols to create a high-speed
serial interface. The GigaBlaze Gflx cores are optimally designed for
use as a physical layer for high-speed protocols including Fibre Channel,
PCI Express and 10 Gigabit Ethernet standards. Multiple GigaBlaze cores
can be integrated into a single ASIC. Combined with other LSI Logic standards-based
cores such as the Merlin Fibre Channel controller, ARM processors and
XGXS, the GigaBlaze cores enable a new approach to high-performance, single-chip
solutions for increased differentiation and reduced chip count, power
and cost. Collapse summary This datasheet provides a basic overview of the CW001102 ARM966E-S Microprocessor
Core, including features and benefits, a block diagram, functional unit
overview, list of signals, instruction set summary, functional timing
information, and electrical and mechanical specifications. The CW001102
ARM966E-S Microprocessor Core is a 32-bit microprocessor. It is manufactured
in the G12-l process technology. The core contains the ARM9E-S processor,
instruction and data RAM, a write buffer, an external coprocessor interface,
and an AHB bus interface. The CW001102 supports both the ARM (32-bit)
and Thumb (16-bit) instruction sets, and also executes the ARM9E instruction
extensions. Collapse summary This datasheet provides a basic overview of the CW001102 ARM966E-S Microprocessor
Core, including features and benefits, a block diagram, functional unit
overview, list of signals, instruction set summary, functional timing
information, and electrical and mechanical specifications. The CW001102
ARM966E-S Microprocessor Core is a 32-bit microprocessor. It is manufactured
in the G12-p process technology. The core contains the ARM9E-S processor,
instruction and data RAM, a write buffer, an external coprocessor interface,
and an AHB bus interface. The CW001102 supports both the ARM (32-bit)
and Thumb (16-bit) instruction sets, and also executes the ARM9E instruction
extensions. Collapse summary This datasheet provides a basic overview of the CW001105 ARM966E-S Microprocessor
Core, including features, a block diagram, functional unit overview, list
of signals, instruction set summary, functional timing information, and
electrical specifications. The CW001105 ARM966E-S Microprocessor Core
is a 32-bit microprocessor in the G12-p process technology. It contains
an ARM9E-S processor core, a coprocessor, instruction and data RAM, an
AHB interface, and JTAG/debug logic. The processor uses the ARMv5T architecture,
and supports both the 32-bit ARM and 16-bit Thumb instruction sets. Collapse summary This document is a quick guide that explains how to install your LSI
Logic MegaRAID SATA 300-4X storage adapter in your host system. The adapter
is a half-size storage adapter that provides support for up to four SATA
ports and a high-performance, intelligent PCI-X to Serial ATA interface
with RAID control capabilities. You can install the SATA board on a PCI-X
bus and use it to connect SATA drives to the host computer over a SATA
cable. The SATA 300-4X adapter supports RAID 0, 1, 5, and 10.MegaRAID
SATA storage adapters are an ideal RAID solution for the internal storage
of workgroup, departmental, and entry-level enterprise systems. They offer
a cost-effective way to implement RAID in a server. Collapse summary This document is a quick guide that explains how to install your LSI
Logic MegaRAID SATA 300-8X storage adapter in your host system. The adapter
is a half-size storage adapter that provides support for up to eight SATA
ports and a high-performance, intelligent PCI-X to Serial ATA interface
with RAID control capabilities. You can install the SATA board on a PCI-X
bus and use it to connect SATA drives to the host computer over a SATA
cable. The SATA 300-8X adapter supports RAID 0, 1, 5, 10, and 50.MegaRAID
SATA storage adapters are an ideal RAID solution for the internal storage
of workgroup, departmental, and entry-level enterprise systems. They offer
a cost-effective way to implement RAID in a server. Collapse summary This document is a quick guide that explains how to install your LSI
Logic MegaRAID SATA 300-4X storage adapter in your host system. The adapter
is a half-size storage adapter that provides support for up to four SATA
ports and a high-performance, intelligent PCI-X to Serial ATA interface
with RAID control capabilities. You can install the SATA board on a PCI-X
bus and use it to connect SATA drives to the host computer over a SATA
cable. The SATA 300-4X adapter supports RAID 0, 1, 5, and 10.MegaRAID
SATA storage adapters are an ideal RAID solution for the internal storage
of workgroup, departmental, and entry-level enterprise systems. They offer
a cost-effective way to implement RAID in a server. Collapse summary This document is a quick guide that explains how to install your LSI
Logic MegaRAID SATA 300-8X storage adapter in your host system. The adapter
is a half-size storage adapter that provides support for up to eight SATA
ports and a high-performance, intelligent PCI-X to Serial ATA interface
with RAID control capabilities. You can install the SATA board on a PCI-X
bus and use it to connect SATA drives to the host computer over a SATA
cable. The SATA 300-8X adapter supports RAID 0, 1, 5, 10, and 50.MegaRAID
SATA storage adapters are an ideal RAID solution for the internal storage
of workgroup, departmental, and entry-level enterprise systems. They offer
a cost-effective way to implement RAID in a server. Collapse summary This document is a quick guide that explains how to install your LSI
Logic MegaRAID SATA 300-4X storage adapter in your host system. The adapter
is a half-size storage adapter that provides support for up to four SATA
ports and a high-performance, intelligent PCI-X to Serial ATA interface
with RAID control capabilities. You can install the SATA board on a PCI-X
bus and use it to connect SATA drives to the host computer over a SATA
cable. The SATA 300-4X adapter supports RAID 0, 1, 5, and 10.MegaRAID
SATA storage adapters are an ideal RAID solution for the internal storage
of workgroup, departmental, and entry-level enterprise systems. They offer
a cost-effective way to implement RAID in a server. Collapse summary This document is a quick guide that explains how to install your LSI
Logic MegaRAID SATA 300-8X storage adapter in your host system. The adapter
is a half-size storage adapter that provides support for up to eight SATA
ports and a high-performance, intelligent PCI-X to Serial ATA interface
with RAID control capabilities. You can install the SATA board on a PCI-X
bus and use it to connect SATA drives to the host computer over a SATA
cable. The SATA 300-8X adapter supports RAID 0, 1, 5, 10, and 50.MegaRAID
SATA storage adapters are an ideal RAID solution for the internal storage
of workgroup, departmental, and entry-level enterprise systems. They offer
a cost-effective way to implement RAID in a server. Collapse summary This document is a quick guide that explains how to install your LSI
Logic MegaRAID SATA 300-4X storage adapter in your host system. The adapter
is a half-size storage adapter that provides support for up to four SATA
ports and a high-performance, intelligent PCI-X to Serial ATA interface
with RAID control capabilities. You can install the SATA board on a PCI-X
bus and use it to connect SATA drives to the host computer over a SATA
cable. The SATA 300-4X adapter supports RAID 0, 1, 5, and 10.MegaRAID
SATA storage adapters are an ideal RAID solution for the internal storage
of workgroup, departmental, and entry-level enterprise systems. They offer
a cost-effective way to implement RAID in a server. Collapse summary This document is a quick guide that explains how to install your LSI
Logic MegaRAID SATA 300-8X storage adapter in your host system. The adapter
is a half-size storage adapter that provides support for up to eight SATA
ports and a high-performance, intelligent PCI-X to Serial ATA interface
with RAID control capabilities. You can install the SATA board on a PCI-X
bus and use it to connect SATA drives to the host computer over a SATA
cable. The SATA 300-8X adapter supports RAID 0, 1, 5, 10, and 50.MegaRAID
SATA storage adapters are an ideal RAID solution for the internal storage
of workgroup, departmental, and entry-level enterprise systems. They offer
a cost-effective way to implement RAID in a server. Collapse summary The CoreWare? design program ensures a seamless flow from high-level
description to a working system on a chip, integrating cores, RAM and
user-defined logic for a design optimized for the target application.
This product brief includes information about features, benefits, CoreWare
deliverables and a sample of the LSI CoreWare library. Collapse summary Databahn is the industry's first fully configurable memory controller.
Designed to deliver optimal performance across a wide range of configuration
options, Databahn can be thought of as a "next generation" memory
controller core. Unlike traditional memory controllers, Databahn is designed
for optimal memory transaction processing, and is supported by a complete
configuration and verification platform to ensure fast, efficient implementations
on a wide variety of SoC ASIC designs. Collapse summary The E1110 is a 10/100/1000 BaseT Ethernet media access controller designed
to support copper and fibre networks. Designed on LSI Logic's 0.18-micron
G12 process technology, the E1110 can support applications requiring speeds
ranging from 10 to 1000 Megabits per second (Mbps) on a single platform
and is an ideal solution for a variety of embedded applications to include
switches, routers, servers, and high-performance desktop computing systems.
Collapse summary The LSI Logic ECC Memory Protection Core provides high-performance error
protection for the tightly coupled memories (TCM) of an embedded ARM processor
while providing a significant reduction in die area compared to traditional
error detection or correction solutions. The ECC core is placed between
the TCM interface of the ARM core and the physical memories that make
up the TCMs. Additionally, since it is a member of the CoreWare? IP library
it will have seamless integration within the ASIC design flow. Collapse summary A review of some of the considerations needed to select the right EDA
tool and hardware for your DFT requirements. Collapse summary The EZ4021 MiniRISC core is the world's first 250MHz 64-bit MIPS embedded
processor. Based on the MIPS III R4000 architecture, the EZ4021 EasyMACRO
is an optimized implementation of a synthesizeable core that operates
up to 250MHz under worst-case conditions. Collapse summary Why ASIC Engineering Service firms and organizations should be considered
your business partnership. Collapse summary This datasheet provides a basic overview of the Ethernet PHY-110 Core,
including features and benefits, a block diagram, functional unit overview,
list of signals, and electrical and mechanical specifications. The Ethernet
PHY-110 Core is a single-channel 10/100 Mbit/s Ethernet PHY. The PHY-110
core separates out common channel logic (such as the clock generator),
allowing multiple PHY-110 cores to create multi-channel PHYs that share
such logic, saving space and power. The PHY-110 has MII and SMII interfaces
to the Ethernet MAC, and an MI interface to configuration and status registers.
Collapse summary The E1110 is a Gigabit Ethernet Media Access Controller core supporting
10/100/1000 BaseT and is designed for easy ASIC integration in support
of high speed copper and fiber networks. Collapse summary The CW001010 core is a 100 MHz implementation of the ARM7TDMI-S microprocessor
core, synthesized onto LSI Logics G12P 0.18 micron high performance process
technology. The ARM7TDMI-S, licensed from ARM Limited, is the synthesized
version of the very successful ARM7TDMI architecture. Collapse summary The CW001009 core is a low power implementation of the ARM7TDMI-S microprocessor
core, synthesized onto LSI Logics G12L 0.18 micron low leakage process
technology. The ARM7TDMI-S, licensed from ARM Limited, is the synthesized
version of the very successful ARM7TDMI architecture. Collapse summary Collapse summary The FlexCore ARM926EJ-S processor core (from LSI Logic, system-on-chip
(SoC) designers can define their specific needs for instruction and data
cache sizes, instruction and data tightly coupled memories (TCMs) target
process technology, target ASIC libraries (high performance or high density)
and the number of metal routing layers required. Once the customer has
decided on the optimal processor configuration for a particular application,
a design simulation model can be provided within a week, and complete
CoreWare? deliverables within four weeks. Collapse summary The CW001100 processor core is a 200 MHz implementation of the popular
ARM946E-S, with fully configurable cache memories, synthesized onto LSI
Logics G12 0.18 micron high performance process technology. Collapse summary The ARM966E-S processor core System-on-Chip (SoC) designers can define
their specific needs for instruction and data tightly coupled memories
(TCMs), target process technology, target ASIC libraries (high performance
or high density) and the number of metal routing layers required. Collapse summary LSI Logic offers FlexCore MIPS32 4KEc processor cores available on both
our Gflx 0.11 micron (drawn) and G12 0.18 micron (drawn) high performance
process technologies, and fully coingure dto individual customer needs.
The FlexCore MIPS 32 4KEc processor core can define specific needs for
instruction and data cache configurations, target process technology,
taget ASIC libraries (high performance or high density momories depending
on frequency reqs. It is a 32-bit five-stage pipeline, Harvard cache architecture
processor core complete with 16-bit code compression. It is ideally suited
for embedded (SOC) applicated such as networking, printers, set-top boxes,
and consumer electronics. Collapse summary This datasheet provides a basic overview of the G12-p 3.3 V, 4 mA, 5-Volt
Tolerant, Fail-Safe, General Purpose I/O Buffers, including features and
benefits, a block diagram, list of signals, and electrical specifications.
The G12-p 3.3 V, 4 mA, 5-Volt Tolerant, Fail-Safe, General Purpose I/O
Buffers are for use in an ASIC environment. The buffers operate at 3.3
V and are 5 V tolerant; they operate up to 20 MHz with a maximum 4 mA
drive strength. Collapse summary This datasheet provides a basic overview of the G12?-p ATA100 3.3 V,
5-Volt Tolerant, Fail-Safe I/O Buffer, including features and benefits,
a block diagram, functional unit overview, list of signals, and mechanical
specifications. The G12-p ATA100 3.3 V, 5-Volt Tolerant, Fail-Safe I/O
Buffer is a buffer for implementing ATA signaling in an ASIC environment.
Collapse summary This datasheet provides a basic overview of the G12?-p Ultra160 SCSI
Transceiver, including features and benefits, a block diagram, list of
signals, and electrical specifications. The G12-p Ultra160 SCSI Transceiver
are G12-p library cells used to create an Ultra160 SCSI bus in an ASIC
application. These transceivers support both single-ended or low-voltage
differential (LVD) buses. The cells operate at up to 40 MHz. Collapse summary This datasheet provides a basic overview of the G12?-p bd4f5fs601s33
4 mA, 60 MHz, 5-Volt Tolerant, Fail-Safe I/O Buffer, including features
and benefits, a block diagram, list of signals, and electrical specifications.
The G12-p bd4f5fs601s33 Buffer is a 60 MHz, 3.3V bidirectional buffer
for use in an ASIC environment. Collapse summary LSI Logic's DDR cores provide an easy physical layer interface between
customer logic on an ASIC and the data bus of the DDR SDRAM memories.
Available in LSI Logic G12TM (0.18-micron) and Gflx? (0.11-micron) technologies,
the cores are 8 bits wide and support a variety of memories like x4, x8,
x16 and x32-bit wide devices. The cores may be used in parallel to handle
data bus widths of 32 bits (4 cores), 64 bits (8 cores) or even 128 bits
(16 cores). the main function of the cores is to enable the Read and Write
operations and to handle all the tight timing between the data strobe
and the data bits to the DDR SDRAMs in the system. Market applications
for the cores include storage, server platforms, communications, inkjet
printing and graphics. Collapse summary The CW108015 Hydra core is an extremely flexible SerDes, optimized for
RapidChip, and also available for use in standard-cell ASIC designs. This
new SerDes will enable a single RapidChip slice or ASIC core to cover
a broad range of applications for medium to high-speed data transmission
applications. Collapse summary HyperPHY is an LSI Logic CoreWare transceiver technology family designed
for broadband and networking applications for extremely high bandwidth
CMOS ASICs. Collapse summary HyperPHY? is an LSI Logic Coreware? transceiver technology family designed
for broadband and networking applications for extremely high bandwidth
CMOS ASICs. Collapse summary RAID technology is widely used in the data center as a cost effective
remote storage solution. As server performance continues to ramp at the
pace of Moore's Law and storage capacity requirements continue a meteoric
climb, the interconnect for a host server system's connections to storage
arrays is emerging as a critical factor in RAID performance. Collapse summary This user's guide provides a basic overview, installation instructions,
and environmental and electrical specifications for the LSISAS3040X, LSISAS3041X,
LSISAS3041XL, LSISAS3442X, LSISAS3442XL, LSISAS3080X, LSISAS3080XL, LSISAS3800X,
and PCI/PCI-X host adapters. Collapse summary This datasheet provides a basic overview of the LSISAS1064 controller,
including features and benefits, a block diagram, functional unit overview,
list of signals, and mechanical specifications. The LSISAS1064 is a 4-port
SAS controller that supports SAS data transfers of up to 3.0 Gbits/s.
The controller also supports SATA data transfers. The controller supports
up to a 133 MHz, 64-bit PCI-X host interface bus. The LSISAS1064 uses
the Fusion-MPT architecture and supports Integrated RAID. Collapse summary This technical manual provides detailed reference information for the
LSISAS1064, including a functional description, register and signal descriptions,
and physical and electrical specifications. The LSISAS1064 is a 4-port
SAS controller that supports SAS data transfers of up to 3.0 Gbits/s.
The controller also supports SATA data transfers. The controller supports
up to a 133 MHz, 64-bit PCI-X host interface bus. The LSISAS1064 uses
the Fusion-MPT architecture and supports Integrated RAID. Collapse summary This datasheet provides a basic overview of the LSISAS1068 controller,
including features and benefits, a block diagram, functional unit overview,
list of signals, and mechanical specifications. The LSISAS1068 is an 8-port
SAS controller that supports SAS data transfers of up to 3.0 Gbits/s.
The controller also supports SATA data transfers. The controller supports
up to a 133 MHz, 64-bit PCI-X host interface bus. The LSISAS1068 uses
the Fusion-MPT architecture and supports Integrated RAID. Collapse summary This technical manual provides detailed reference information for the
LSISAS1068, including a functional description, register and signal descriptions,
and physical and electrical specifications. The LSISAS1068 is an 8-port
SAS controller that supports SAS data transfers of up to 3.0 Gbits/s.
The controller also supports SATA data transfers. The controller supports
up to a 133 MHz, 64-bit PCI-X host interface bus. The LSISAS1068 uses
the Fusion-MPT architecture and supports Integrated RAID. Collapse summary A paper written by one of Mint Technology’s top DFT (Design For Test)
engineers outlining the reasons for ASIC projects to develop a Manufacturing
Test Specification. The paper proposes a standard format Collapse summary This quick installation guide describes how to install the MegaRAID LSIiBBU01
Intelligent Battery Backup Unit on a MegaRAID SATA 300 PCI-X to Serial
ATA storage adapter. It includes installation diagrams, and it lists the
basic hardware specifications for the MegaRAID LSIiBBU01. Collapse summary This document is a quick guide that explains how to install your LSI
Logic MegaRAID SATA 300-4X storage adapter in your host system. The adapter
is a half-size storage adapter that provides support for up to four SATA
ports and a high-performance, intelligent PCI-X to Serial ATA interface
with RAID control capabilities. You can install the SATA board on a PCI-X
bus and use it to connect SATA drives to the host computer over a SATA
cable. The SATA 300-4X adapter supports RAID 0, 1, 5, and 10. MegaRAID
SATA storage adapters are an ideal RAID solution for the internal storage
of workgroup, departmental, and entry-level enterprise systems. They offer
a cost-effective way to implement RAID in a server. Collapse summary This document is a quick guide that explains how to install your LSI
Logic MegaRAID SATA 300-4X storage adapter in your host system. The adapter
is a half-size storage adapter that provides support for up to four SATA
ports and a high-performance, intelligent PCI-X to Serial ATA interface
with RAID control capabilities. You can install the SATA board on a PCI-X
bus and use it to connect SATA drives to the host computer over a SATA
cable. The SATA 300-4X adapter supports RAID 0, 1, 5, and 10.MegaRAID
SATA storage adapters are an ideal RAID solution for the internal storage
of workgroup, departmental, and entry-level enterprise systems. They offer
a cost-effective way to implement RAID in a server. Collapse summary This document is a quick guide that explains how to install your LSI
Logic MegaRAID SATA 300-8X storage adapter in your host system. The adapter
is a half-size storage adapter that provides support for up to eight SATA
ports and a high-performance, intelligent PCI-X to Serial ATA interface
with RAID control capabilities. You can install the SATA board on a PCI-X
bus and use it to connect SATA drives to the host computer over a SATA
cable. The SATA 300-8X adapter supports RAID 0, 1, 5, 10, and 50. MegaRAID
SATA storage adapters are an ideal RAID solution for the internal storage
of workgroup, departmental, and entry-level enterprise systems. They offer
a cost-effective way to implement RAID in a server. Collapse summary This document is a quick guide that explains how to install your LSI
Logic MegaRAID SATA 300-8X storage adapter in your host system. The adapter
is a half-size storage adapter that provides support for up to eight SATA
ports and a high-performance, intelligent PCI-X to Serial ATA interface
with RAID control capabilities. You can install the SATA board on a PCI-X
bus and use it to connect SATA drives to the host computer over a SATA
cable. The SATA 300-8X adapter supports RAID 0, 1, 5, 10, and 50.MegaRAID
SATA storage adapters are an ideal RAID solution for the internal storage
of workgroup, departmental, and entry-level enterprise systems. They offer
a cost-effective way to implement RAID in a server. Collapse summary This technical manual provides detailed reference information for the
MiniRISC EZ4021-FC Building Blocks, including a functional description,
register and signal descriptions, and functional timing information. The
MiniRISC EZ4021-FC Building Blocks are a microprocessor components for
use with the EZ4021-FC microprocessor core. The building blocks include
an SDRAM controller, QuickBus, and External Bus Controller. Collapse summary This datasheet provides a basic overview of the MiniRISC EZ4021-FC EasyMACRO
Microprocessor, including features and benefits, a block diagram, functional
unit overview, list of signals, and instruction set summary. The EZ4021-FC
is a 64-bit microprocessor subsystem that executes the MIPS III instruction
set. Collapse summary This technical manual provides detailed reference information for the
MiniRISC EZ4021-FC EasyMACRO microprocessor subsystem including a functional
description, register and signal descriptions, instruction set, physical
and electrical specifications, and functional timing information. The
MiniRISC EZ4021-FC EasyMACRO is a 64-bit Microprocessor subsystem that
is manufactured in the G12 process technology and executes the MIPS III
instruction set. Collapse summary A 2 page primer on Mint Technology - our history, capabilities, and value
proposition. Collapse summary An overview of Mint Technology - history, business practices, and capabilities.
Closing with the reasons to use Mint Technology as your Engineering Services
Partner. Collapse summary A day in the life of a DFT Engineer... Collapse summary Collapse summary LSI Logic's 16-lane PCI Express? Physical (PHY)and Link Layer cores provide
a PCI-Express compliant physical and data link layer functionality*. As
a part of the LSI Logic's CoreWare? library, the cores are available in
LSI Logic's 0.11μm technology for standard cell ASIC as well as the RapidChip?
platforms. These feature-rich cores are optimized for a 16 lane operation.
They provide a total bandwidth of 8 Gbytes/s and can easily be integrated
into SOC designs.These cores can be used in many storage, communications,
consumer, and industrial platforms. Collapse summary LSI Logic's 8-lane PCI Express? Physical (PHY)and Link Layer cores provide
a PCI-Express-compliant Physical and data link layer blocks*. As a part
of the LSI Logic's CoreWare? library, the cores are available in LSI Logic's
0.11μm technology for standard cell ASIC as well as the RapidChipTM platforms.
These feature-rich cores are optimized for 8-lane operation. They provide
a total bandwidth of 4 Gbytes/s and can easily be integrated into SOC
designs. (see Figure.1) These cores can be used in many storage, communications,
consumer, and industrial platforms. Collapse summary An EETimes editorial written by Mint Technology that dispels the notion
that a push button flow can - or will ever - exist. Collapse summary Collapse summary The LSI Logic DDR-1 physical layer core (PHY core) for RapidChip? Platform
ASIC provides an integration friendly physical layer interface between
the memory controller logic of the ASIC and the data and address busses
of DDR-1 SDRAM memory. This physical layer ensures seamless integration
with the RapidChip Platform ASIC design flow tools. Collapse summary LSI Logic's RLDRAM-II address and data path cores and I/O buffer provide
an easy physical layer interface between the customer logic of the ASIC
and the data and address busses of the RLDRAM-II memory. (See Figure1.)
The cores and I/O are available in G flx Technology (0.11um). The data
path core is 18 bits wide and multiple of these cores can be used in parallel
to handle data bus widths of 36 bits (2cores), 72bits (4cores) or even
144bits(8cores). The address core is 22 bits wide. The main function of
the cores is to enable memory READ and WRITE operations and provide an
easy interface for the customer logic in the single data rate domain thereby
taking the pain away from handling the tight timing margins associated
with high performance double data rate RLDRAM interfaces. Market applications
of the cores include Communications and Storage platforms. Collapse summary How Rapid Prototyping with FPGAs goes hand in hand with developing complex
SoC ASICs and can help pull in your time to market. Collapse summary LSI Logic's DDR-1 physical layer core (PHY core) provides an integration-friendly
physical layer interface between the memory controller logic of the ASIC
and the data and address busses of the DDR-1 SDRAM memory. This RapidChip?
physical layer core, part of the LSI Logic RapidChip? Platform ASIC design
program, integrates the necessary address and data path interfaces with
additional logic while supporting data widths in multiples of 8 (e.g.,
8 bits, 16 bits, 32 bits, 72 bits and 144 bits). The CW761041 PHY core
is designed in 0.18-micron technology and is based on diffused data-path
and Master delay modules. The CW000722 PHY core is designed in 0.11-micron
technology and is based on R-cell datapath and Master delay modules. Both
cores are part of LSI Logic CoreWare? design program and are available
for immediate design-ins. Collapse summary The RapidChip? Foundation Platform ASIC IP-rich slices are designed to
deliver fast time to market and much reduced engineering costs. Review
the capabilities of the RapidChip Foundation Slices and select the one
with the right mix of pre-designed and pre-fabricated functionality for
your design. Collapse summary Licensing Agreement for the RapidWorx Design Tool Collapse summary The RapidWorx? Design Kit encompasses a complete RTL to placed-gates
design flow. Collapse summary Collapse summary The SpeedBlazer consist of four separate full duplex serializers/deserializers
(SerDes). Based on LSI Logic's GigaBlaze? Technology, each channel of
the device is designed to transmit and receive serial data at up to 3.125
Gbps through each channel. These high speed gigabit transceivers provide
parallel-to-serial and serial-to-parallel conversion, clock recovery,
and byte alignment. In addition, when the devices, resynchronization with
the local clock, and lane alignment, per the intent of the 10 Gigabit
IEEE standard. Collapse summary The StreamSlice RapidChip? Platform ASIC is designed to meet the needs
of today's high performance 10G communications systems. Collapse summary A reprint of a Mint Technology article originally published in Test &
Measurement World. An outline of why and how communications between ASIC
design engineers and test engineers is the key to a successful ASIC project.
Collapse summary The processor system for ARM926EJ-S? (CW001200) from LSI Logic is an
OS-ready system that is available for both standard-cell ASIC and RapidChip?
Platform ASICs. In RapidChip Platform ASIC, the processor system fits
seamlessly with the diffused ARM926EJ-S in the Foundation slices and with
the processor Landing Zone? region built into all the RapidChip Integrator
slices. The processor system significantly reduces design time, complexity
and risk for SoC customers providing them the ability to get their products
manufactured quickly and at low cost. Collapse summary An EETimes article written by Mint Technology describing how Mint’s verification
environments and methodology allow extensive reusability. Reusability
is the key to meeting aggressive time to market goals of most projects.
Collapse summary This user's guide provides detailed reference and usage information for
the TinyRISC BDMR4102 Evaluation Board, including a functional description,
installation instructions, programming information, and a bill of materials/list
of deliverables. The TinyRISC BDMR4102 Evaluation Board is the evaluation
board for the LR4102 reference device. Collapse summary This user's guide provides detailed reference and usage information for
the TinyRISC BDMR4103 Evaluation Board, including a functional description,
installation instructions, programming information, and a bill of materials/list
of deliverables. The BDMR4103 is the evaluation board for the LR4103 reference
device. Collapse summary This datasheet provides a basic overview of the TinyRISC EZ4102 EasyMACRO
microprocessor subsystem, including features and benefits, a block diagram,
functional unit overview, list of signals, and instruction set summary.
The EZ4102 is a 32-bit MIPS microprocessor subsystem implemented in the
G11 process technology. Collapse summary This technical manual provides detailed reference information for the
TinyRISC EZ4102 EasyMACRO microprocessor subsystem and the FBusMACRO bus
controller module. It includes functional descriptions, signal descriptions,
register descriptions, instruction set description, and functional timing
information. The EZ4102 is a 32-bit microprocessor that executes the MIPS
instruction set. The FBusMACRO is a bus controller module that transfers
data between the microprocessor's internal bus and an external device.
Collapse summary This addendum to the technical manual provides the physical and electrical
characteristics of the TinyRISC EZ4102 EasyMACRO? microprocessor subsystem
and the FBusMACRO? bus controller module. The EZ4102 is a 32-bit microprocessor
that executes the MIPS instruction set. The FBusMACRO is a bus controller
module that transfers data between the microprocessor脙垄脗聙脗聂s internal
bus and an external device. Collapse summary This datasheet provides a basic overview of the TinyRISC EZ4103 EasyMACRO
microprocessor, including features and benefits, a block diagram, functional
unit overview, list of signals, and instruction set summary. The EZ4103
is a 32-bit MIPS microprocessor manufactured in G12 process technology.
Collapse summary The addendum provides the physical and electrical characteristics of
the TinyRISC EZ4103 EasyMACRO Microprocessor and the FBusMACRO bus controller
module. The EZ4103 is a 32-bit MIPS microprocessor manufactured in G12
process technology. The FBusMACRO bus controller module transfers data
between the microprocessor芒聙聂s internal bus and external devices. Collapse summary This technical manual provides detailed reference information for the
TinyRISC EZ4103 EasyMACRO microprocessor and the FBusMACRO bus controller
module. It includes a functional description, register and signal descriptions,
and functional timing information. The EZ4103 is a 32-bit MIPS microprocessor
subsystem implemented in the G12 process technology. The FBusMACRO bus
controller module transfers data between the microprocessor’s internal
bus and external devices. Collapse summary This datasheet provides a basic overview of the TinyRISC LR4102 microprocessor,
including features and benefits, a block diagram, functional unit overview,
list of signals, register summary, instruction set summary, functional
timing information, and electrical and mechanical specifications. The
LR4102 is a 32-bit microprocessor that executes the MIPS instruction set
and is manufactured in G11 process technology. Collapse summary This technical manual provides detailed reference information for the
TinyRISC LR4102 Microprocessor, including a functional description, register
and signal descriptions, and functional timing information. The LR4102
is a 32-bit microprocessor that executes the MIPS instruction set and
is manufactured in the G11 process technology. Collapse summary The CoreWare? CW000026 Multi-Port Host (MPH) core is a highly optimized,
low gate count IP core that allows system developers to implement compact,
cost effective, low power USB-based SoC solutions. Collapse summary The USB Function Core is a flexible and configurable core interfacing
a peripheral function to the Universal Serial Bus and enabling the design
of highly integrated peripheral single-chip systems. Combining the USB
Function core and LSI Logic's USB transceiver I/Os with other CoreWare?
cores and customer-defined logic creates cost-effective solutions for
USB peripherals such as digital cameras, scanners, ISDN modems and multifunction
peripherals. Collapse summary The USB Host Core, a component of LSI Logic's comprehensive USB solution
set, is a flexible and configurable core that manages and generates the
Universal Serial Bus, providing support of USB peripherals in highly integrated
embedded systems. The USB Host Core simplifies the design of USB-enabled
embedded systems and system logic. Collapse summary
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